The present invention is related to input/output buffer circuits in integrated circuits and, more specifically, to buffer circuits which have various optionally programmable operating characteristics and which have certain test capabilities.
In an integrated circuit, input output buffer circuits lie electrically between the rest of the integrated circuit and the external environment, i.e., the system in which the integrated circuit is placed. As the name implies, these circuits "buffer" or condition signals from the external environment to the integrated circuit and signals from the integrated circuit to the external environment. In nearly all integrated circuits these buffer circuits are designed with a particular external environment in mind. Thus a redesign is required if the integrated circuit is to be relocated in a different system having different requirements. It is highly desirable that input/output buffer circuits be easily adaptable to different external environments.
Furthermore, a recent requirement upon input/output buffer circuits is testability. As integrated circuits and the systems in which they are located have become more complex and densely packed, the testing of the integrated circuits have become more complex and difficult. One proposed solution is the IEEE standard 1149.1 for boundary scan testing in which the input/output buffer circuits form a serial scan chain over which test data can be passed. Test data can be scanned into the integrated circuit over the serial chain between the buffer circuits, processed by the integrated circuit and then scanned out over the chain. The changes to the processed test data yield the desired test information about the integrated circuit.
However, the IEEE standard 1149.1 requires circuits in the input/output buffer to perform the scanning function which are additional to the circuits for input and output functions. This added "overhead" to an input/output buffer circuit occupies valuable space on the semiconductor substrate on which the integrated circuit is formed and typically slows the operating speed of the buffer circuit.
It is thus desirable that an input/output buffer circuit have circuits which can perform the input/output and the test functions in a consolidated fashion to reduce the space occupied by the buffer circuit and which can function at high speeds so as to avoid any denigration of performance.
The present invention is able to achieve all these goals and more.